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surveys:synthesis [2011/04/19 16:31] jobstman |
surveys:synthesis [2011/04/19 16:54] jobstman |
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| * Logic synthesis (RTL to gate level, net list to layout,...) | * Logic synthesis (RTL to gate level, net list to layout,...) | ||
| * Synthesis from logical specifications | * Synthesis from logical specifications | ||
| - | * Domain specific synthesizer: | + | * Model-based design and other domain specific synthesizer: |
| * parser generators (YACC) | * parser generators (YACC) | ||
| * generator for statistical analyzers (AutoBayes Synthesis System, Johann M. Schumann, NASA - Moffett Field) | * generator for statistical analyzers (AutoBayes Synthesis System, Johann M. Schumann, NASA - Moffett Field) | ||
| - | * ... | + | * Matlab Simulink from MathWorks (based on a synchronous dataflow language, generates C/C++ code) |
| + | * SCADE Suite from Esterel Technologies (Systems are described using a synchronous language, generates C/C++ code) | ||
| + | * Bluespec compiler (HDL based on rules, each rule is executed automatically, designs have no explicit clock, generates Verilog code) | ||
| + | * BIP compiler (Systems are describe using extended automata and synchronization constructs, generates C/C++ code) | ||
| + | * ... | ||
| + | |||
| + | In the following we will focus on synthesis from logical specifications. | ||
| ====== Program synthesis from logical specification ====== | ====== Program synthesis from logical specification ====== | ||