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surveys:synthesis [2011/04/19 16:29] jobstman |
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| - | ====== Program synthesis ====== | + | ====== Program synthesis (SURVEY UNDER CONSTRUCTION) ====== |
| - | In computer science, program synthesis refers to the development of a program or a digital design from a set of desired properties. | + | We use the term **program synthesis** to refer to the development of a program or a digital design from a set of desired properties. |
| These properties can be described in various ways, e.g., by a set of logical formulas or a mathematical model, by another program that is | These properties can be described in various ways, e.g., by a set of logical formulas or a mathematical model, by another program that is | ||
| written in a more abstract programming language. Synthesis is the counterpart to program analysis, which tries to extract a set of properties or a model from a given program or digital design, or program verification, which tries to establish a relationship between a set of properties and the given program or circuit. | written in a more abstract programming language. Synthesis is the counterpart to program analysis, which tries to extract a set of properties or a model from a given program or digital design, or program verification, which tries to establish a relationship between a set of properties and the given program or circuit. | ||
| - | The set of desired properties are usually called the //specification of the system// and the constructed system is referred as the | + | The set of desired properties are usually called the **specification of the system** and the constructed system is referred as the |
| - | //implementation of the specification.// | + | **implementation of the specification.** |
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| * Logic synthesis (RTL to gate level, net list to layout,...) | * Logic synthesis (RTL to gate level, net list to layout,...) | ||
| * Synthesis from logical specifications | * Synthesis from logical specifications | ||
| - | * Domain specific synthesizer: | + | * Model-based design and other domain specific synthesizer: |
| * parser generators (YACC) | * parser generators (YACC) | ||
| * generator for statistical analyzers (AutoBayes Synthesis System, Johann M. Schumann, NASA - Moffett Field) | * generator for statistical analyzers (AutoBayes Synthesis System, Johann M. Schumann, NASA - Moffett Field) | ||
| - | * ... | + | * Matlab Simulink from MathWorks (based on a synchronous dataflow language, generates C/C++ code) |
| + | * SCADE Suite from Esterel Technologies (Systems are described using a synchronous language, generates C/C++ code) | ||
| + | * Bluespec compiler (HDL based on rules, each rule is executed automatically, designs have no explicit clock, generates Verilog code) | ||
| + | * BIP compiler (Systems are describe using extended automata and synchronization constructs, generates C/C++ code) | ||
| + | * ... | ||
| + | |||
| + | In the following we will focus on synthesis from logical specifications. | ||
| ====== Program synthesis from logical specification ====== | ====== Program synthesis from logical specification ====== | ||